/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) ASPEED Technology Inc.
 * Ryan Chen <ryan_chen@aspeedtech.com>
 *
 */

#ifndef _ASPEED_PLATFORM_H_
#define _ASPEED_PLATFORM_H_

#define AST_PLL_25MHZ			25000000
#define AST_PLL_24MHZ			24000000
#define AST_PLL_12MHZ			12000000

/*********************************************************************************/
#if defined(CONFIG_TARGET_ASPEED_AST2700)
#define ASPEED_AHBC0_BASE		0x12000000
#define ASPEED_CPU_SCU_BASE		0x12C02000
#define ASPEED_CPU_REVISION_ID		0x12C02000
#define ASPEED_CPU_HW_STRAP1		0x12C02010
#define ASPEED_CPU_HW_STRAP1_CLR	0x12C02014
#define ASPEED_CPU_RESET_LOG1		0x12C02050
#define ASPEED_CPU_RESET_LOG2		0x12C02060
#define ASPEED_CPU_RESET_LOG3		0x12C02070
#define ASPEED_CPU_CA35_REL		0x12C0210C
#define ASPEED_CPU_CA35_RVBAR0		0x12C02110
#define ASPEED_CPU_CA35_RVBAR1		0x12C02114
#define ASPEED_CPU_CA35_RVBAR2		0x12C02118
#define ASPEED_CPU_CA35_RVBAR3		0x12C0211c
#define ASPEED_CPU_HPLL			0x12c02300
#define ASPEED_CPU_HPLL2		0x12c02304
#define ASPEED_CPU_MPLL			0x12c02310
#define ASPEED_CPU_MPLL2		0x12c02314
#define ASPEED_CPU_SMP_EP0		0x12C02780
#define ASPEED_CPU_SMP_EP1		0x12C02788
#define ASPEED_CPU_SMP_EP2		0x12C02790
#define ASPEED_CPU_SMP_EP3		0x12C02798
#define ASPEED_MAC_COUNT		3
#define ASPEED_DRAM_BASE		0x80000000
#define ASPEED_SRAM_BASE		0x10000000
#define ASPEED_SRAM_SIZE		0x20000
#define ASPEED_FMC_REG_BASE		0x14000000
#define ASPEED_SPI0_REG_BASE		0x14010000
#define ASPEED_SPI1_REG_BASE		0x14020000
#define ASPEED_FMC_CS0_BASE		0x20000000
#define ASPEED_AHBC1_BASE		0x140b0000
#define ASPEED_IO_SCU_BASE		0x14C02000
#define ASPEED_IO_REVISION_ID		0x14C02000
#define   CHIP_AST2700A1_ID_SHIFT	(16)
#define   CHIP_AST2700A1_ID_MASK	GENMASK(17, 16)
#define ASPEED_IO_HW_STRAP1		0x14C02010
#define ASPEED_IO_RESET_LOG1		0x14C02050
#define ASPEED_IO_RESET_LOG2		0x14C02060
#define ASPEED_IO_RESET_LOG3		0x14C02070
#define ASPEED_IO_RESET_LOG4		0x14C02080
#define ASPEED_IO_MISC			0x14c020c0
#define   ASPEED_IO_MISC_SIO_LTPI1_EN	BIT(4)
#define   ASPEED_IO_MISC_SIO_LTPI_EN	BIT(3)
#define ASPEED_IO_INTC_BASE		0x14C18000
#define ASPEED_LTPI0_BASE		0x14c34000
#define ASPEED_LTPI1_BASE		0x14c35000
#define ASPEED_WDT_BASE			0x14c37000
#define ASPEED_WDTA_BASE		0x14c37400
#define ASPEED_HASH_BUFFER		0x14baf800
#else
#err "Unrecognized Aspeed platform."
#endif

#endif
